Please title this page. (sxdefs

NOLIST ;============================================================================== ; : ; This program is available from: : ; : ; Rho Enterprises : ; 4100 W. Colfax Ave. : ; Box 33 : ; Denver, CO 80204 : ; : ; Phone: 720-359-1467 Email: info@rhoent.com : ; : ; http://www.rhoent.com/ : ; : ;============================================================================== ; ;SXDEFS.INC by Loren Blaney and Richard Ottosen 14-FEB-2000 ; ; ;Scenix SX Definitions for Microchip MPASM. ; ;REVISIONS: ;FEB-23-98, Released. ;MAR-21-98, Added ID label. Corrected XT & HS defs by swapping them. ; Removed ASCII defs. New STATUS defs. ;MAR-27-98, Added PAGEA, BANKA, FCALL, FGOTO, SKIP. ;APR-13-98, Added CSA, CSBE (etc.) macros. Enclose all arguments in parentheses. ; Indent macros. ;APR-23-98, Changed some comments. ;OCT-4-98, Removed "RADIX DEC", added processor type based on SX FUSEX bits, ; added Trim bits to FUSEX and other cleanup. R.O. ;OCT-14-98 BOSC defaults to a "1". ;NOV-4-98, Revised Pins, Trim bits and BOSC in DEVICE equates, removed some ; inversions. R.O. ;SEP-11-99, Added warnings and messages to BANK and PAGE macros. R.O. ;9-JAN-2000, Changed ID bytes to leave unused bits as ones. R.O. ;12-JAN-2000, Made variables in macros local. R.O. ;14-FEB-2000, Cleanup. R.O. ;Define special function registers: INDF EQU 00h ;used for indirects thru fsr RTCC EQU 01h ;real time clock/counter PCL EQU 02h ;low 8 bits of PC STATUS EQU 03h ;status bits FSR EQU 04h ;file select register PORTA EQU 05h ;I/O ports PORTB EQU 06h ;supports multi-input wake-up (MIWU) PORTC EQU 07h ;Define STATUS register bits: CF EQU 0 ;carry DCF EQU 1 ;digit carry ZF EQU 2 ;zero PDF EQU 3 ;sleep power down (true low) TOF EQU 4 ;watchdog time out (true low) PA0 EQU 5 ;page select (LSB) PA1 EQU 6 ;page select PA2 EQU 7 ;page select (MSB) ;Define port control registers: TRISX EQU 0Fh ;tristate (1=input, 0=output) PLP EQU 0Eh ;pullup (1=none, 0=20k) LVL EQU 0Dh ;level (1=TTL, 0=CMOS) ST EQU 0Ch ;Schmitt trigger (1=disabled, 0=enabled) WKEN EQU 0Bh ;wake up (1=disabled, 0=enabled) WKED EQU 0Ah ;wake up edge (1=falling, 0=rising) WKPND EQU 09h ;wake up pending (1=pending, 0=none) CMP EQU 08h ;comparator bit: 0=result, 6=output, 7=enabled ;Define device symbols for configuration words (FUSE & FUSEX): OSCRC EQU b'00' ;external RC network (default, inverted) OSCHS EQU b'01' ;high speed external crystal/resonator OSCXT EQU b'10' ;normal external crystal/resonator OSCLP EQU b'11' ;low power external crystal/resonator WATCHDOG EQU 1 << 2 ;watchdog timer enabled ; default to disabled PROTECT EQU 1 << 3 ;code protect enabled (inverted) ; default is to disable code protect OSC4MHZ EQU b'1000' << 4 ;internal 4MHz OSC2MHZ EQU b'1001' << 4 ;internal 2MHz OSC1MHZ EQU b'1010' << 4 ;internal 1MHz OSC500KHZ EQU b'1011' << 4 ;internal 500KHz OSC250KHZ EQU b'1100' << 4 ;internal 250KHz OSC125KHZ EQU b'1101' << 4 ;internal 125KHz OSC62KHZ EQU b'1110' << 4 ;internal 62.5KHz OSC31KHZ EQU b'1111' << 4 ;internal 31.25KHz STACKX EQU 1 << d'8' ;stack is extended to 8 levels (inverted) ; default to 2 levels OPTIONX EQU 1 << d'9' ;extend option register to 8 bits (inverted) ; default to 6 bits SYNC EQU 1 << d'10' ;input syncing enabled (inverted) ; default to disabled TURBO EQU 1 << d'11' ;turbo mode enabled (inverted) ; default to disabled PAGES1 EQU b'00' << d'12' ;default PAGES2 EQU b'01' << d'12' PAGES4 EQU b'10' << d'12' PAGES8 EQU b'11' << d'12' BANKS1 EQU b'00' << d'14' ;default BANKS2 EQU b'01' << d'14' BANKS4 EQU b'10' << d'14' BANKS8 EQU b'11' << d'14' BOR40 EQU b'11' << d'16' ;4.0V brownout reset BOR25 EQU b'10' << d'16' ;2.5 BOR13 EQU b'01' << d'16' ;1.3 ;BOR00 EQU b'00' << d'16' ;disabled (default, inverted) CARRYX EQU 1 << d'18' ;ADDWF & SUBWF use carry input (inverted) ; default is to ignore carry in PRE7 EQU 1 << d'19' ;for changing the preset FUSEX bit 7 (inverted) ; default is no change ;for modifying factory IRC calibration TRIM0 EQU b'0000' << d'20' ;highest frequency TRIM3 EQU b'0001' << d'20' ; TRIM6 EQU b'0010' << d'20' ; TRIM9 EQU b'0011' << d'20' ; about 3% per step TRIM12 EQU b'1000' << d'20' ; TRIM15 EQU b'1001' << d'20' ; TRIM18 EQU b'1010' << d'20' ; TRIM21 EQU b'1011' << d'20' ;lowest frequency (default) PINS18 EQU b'0' << d'22' ;default to 18 pin PINS28 EQU b'1' << d'22' _INVERT EQU 0F0F8Bh ;the default looks like a PIC16C54 _DEVICE SET DEVICE ^ _INVERT _FUSE SET _DEVICE & 0FFFh _FUSEX SET _DEVICE >> d'12' ;Select a Microchip processor enough like the Scenix processor to satisfy the ; assembler _PINS SET (_FUSEX & 0400h) >> d'10' _ROM SET _FUSEX & 003h ;Define macros for new Scenix instructions: __NowBank SET 0 ;Default to bank 0 for both past and present __LastBank SET 0 ; bank (like the H/W should but doesn't) __NowPage SET 7 ;Default to top page for both __LastPage SET 7 ; past and present page (like the H/W does) ;Define macro for ID label. Example: ; ID 'S', 'X', '-', 'D', 'e', 'm', 'o', ' ' ID MACRO A,B,C,D,E,F,G,H ;set up ID label NOLIST LOCAL _A,_B,_C,_D,_E,_F,_G,_H _A SET A _B SET B _C SET C _D SET D _E SET E _F SET F _G SET G _H SET H ERRORLEVEL -220 ;don't display "address exceeds range" warning ORG 1000h ;*** DATA (_A>>4)&0Fh, A&0Fh ;Unused bits are cleared ; DATA (_B>>4)&0Fh, B&0Fh ; DATA (_C>>4)&0Fh, C&0Fh ; DATA (_D>>4)&0Fh, D&0Fh ; DATA (_E>>4)&0Fh, E&0Fh ; DATA (_F>>4)&0Fh, F&0Fh ; DATA (_G>>4)&0Fh, G&0Fh ;*** DATA (_H>>4)&0Fh, H&0Fh DATA (_A>>4)|0FF0h, A|0FF0h ;Unused bits are set DATA (_B>>4)|0FF0h, B|0FF0h DATA (_C>>4)|0FF0h, C|0FF0h DATA (_D>>4)|0FF0h, D|0FF0h DATA (_E>>4)|0FF0h, E|0FF0h DATA (_F>>4)|0FF0h, F|0FF0h DATA (_G>>4)|0FF0h, G|0FF0h DATA (_H>>4)|0FF0h, H|0FF0h ERRORLEVEL +220 ;restore warning message ORG 0 LIST ENDM ERRORLEVEL -220 ;don't display "address exceeds range" warning ORG 1010h LIST DATA _FUSE ;configuration bits (TURBO, SYNC, OPTIONX, etc.) DATA _FUSEX ; (PINS, CARRYX, BOR40, BANKS, PAGES) NOLIST ERRORLEVEL +220 ;restore warning message ORG 0 LIST

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